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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. general description the MAX1652?ax1655 are high-efficiency, pulse- width-modulated (pwm), step-down dc-dc controllers in small qsop packages. the max1653/max1655 also come in 16-pin narrow so packages that are pin- compatible upgrades to the popular max797. improve- ments include higher duty-cycle operation for better dropout, lower quiescent supply currents for better light-load efficiency, and an output voltage down to 1v (max1655). the MAX1652?ax1655 achieve up to 96% efficiency and deliver up to 10a using a unique idle mode syn- chronous-rectified pwm control scheme. these devices automatically switch between pwm operation at heavy loads and pulse-frequency-modulated (pfm) operation at light loads to optimize efficiency over the entire out- put current range. the max1653/max1655 also feature logic-controlled, forced pwm operation for noise-sensi- tive applications. all devices operate with a selectable 150khz/300khz switching frequency, which can also be synchronized to an external clock signal. both external power switch- es are inexpensive n-channel mosfets, which provide low resistance while saving space and reducing cost. the MAX1652 and max1654 have an additional feed- back pin that permits regulation of a low-cost second output tapped from a transformer winding. the MAX1652 provides an additional positive output. the max1654 provides an additional negative output. the MAX1652?ax1655 have a 4.5v to 30v input volt- age range. the MAX1652/max1653/max1654? output range is 2.5v to 5.5v while the max1655? output range extends down to 1v. an evaluation kit (max1653evkit) is available to speed designs. applications notebook computers pdas cellular phones hand-held computers handy-terminals mobile communicators distributed power ____________________________features ? 96% efficiency ? small, 16-pin qsop package (half the size of a 16-pin narrow so) ? pin-compatible with max797 (max1653/max1655) ? output voltage down to 1v (max1655) ? 4.5v to 30v input range ? 99% duty cycle for lower dropout ? 170? quiescent supply current ? 3? logic-controlled shutdown ? dual, n-channel, synchronous-rectified control ? fixed 150khz/300khz pwm switching, or synchronized from 190khz to 340khz ? programmable soft start ? low-cost secondary outputs (MAX1652/max1654) MAX1652?ax1655 high-efficiency, pwm, step-down dc-dc controllers in 16-pin qsop ________________________________________________________________ maxim integrated products 1 19-1357; rev 1; 7/98 evaluation kit available ordering information selection guide pin configurations appear at end of data sheet. idle mode is a trademark of maxim integrated products. part feedback voltage (v) special feature compatibility MAX1652 2.5 regulates positive secondary voltage (such as +12v) same pin order as max796, but smaller package max1653 2.5 logic-controlled, low-noise mode pin-compatible with max797 max1654 2.5 regulates negative secondary voltage (such as -5v) same pin order as max799, but smaller package max1655 1 low output volt- ages (1v to 5.5v); logic-controlled, low-noise mode pin compatible with max797 (except for feed- back voltage) part MAX1652 eee -40? to +85? temp. range pin-package 16 qsop max1653eee -40? to +85? 16 qsop max1654 eee -40? to +85? 16 qsop max1653 ese -40? to +85? 16 narrow so max1655 ese -40? to +85? 16 narrow so max1655eee -40? to +85? 16 qsop
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = +15v, gnd = pgnd = 0v, sync = ref, i vl = i ref = 0a, t a = 0 c to +85 c , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd .............................................................. -0.3v to +36v gnd to pgnd ....................................................... -0.3v to +0.3v vl to gnd ................................................................ -0.3v to +6v bst to gnd ............................................................ -0.3v to +36v dh to lx ..................................................... -0.3v to (bst + 0.3v) lx to bst .................................................................. -6v to +0.3v shdn to gnd ............................................... -0.3v to (v+ + 0.3v) sync, ss, ref, secfb, skip, fb to gnd ... -0.3v to (vl + 0.3v) dl to pgnd .................................................. -0.3v to (vl + 0.3v) csh, csl to gnd .................................................... -0.3v to +6v vl short circuit to gnd .............................................. momentary ref short circuit to gnd ........................................... continuous vl output current ............................................... +50ma to -1ma ref output current ............................................... +5ma to -1ma continuous power dissipation (t a = +70 c) so (derate 8.70mw/ c above +70 c) ....................... 696mw qsop (derate 8.3mw/ c above +70 c) .................... 667mw operating temperature range max165_e_e .................................................. -40 c to +85 c storage temperature range ............................. -65 c to +160 c lead temperature (soldering, 10sec) ............................. +300 c rising edge, falling edge hysteresis = 60mv rising edge, falling edge hysteresis = 50mv shdn = 2v, 0 < i vl < 25ma, 5.5v < v+ < 30v rising edge, falling edge, hysteresis = 22mv (max1654) csh - csl, negative csh - csl, positive falling edge, rising edge, hysteresis = 22mv (MAX1652) 6v < v+ < 30v 25mv < (csh - csl) < 80mv 0 < (csh - csl) < 80mv, fb = vl, 6v < v+ < 30v, includes line and load regulation external resistor divider v ss = 4v 0 < (csh - csl) < 80mv v ss = 0v conditions v 4.2 4.5 4.7 vl/csl switchover voltage v 3.8 3.9 4.0 vl fault lockout voltage v 4.7 5.0 5.3 vl output voltage -0.05 0 0.05 v 2.45 2.50 2.55 secfb regulation setpoint ma 2.0 ss fault sink current a 2.5 4.0 6.5 ss source current v 4.5 30 input supply range -50 -100 -160 mv 80 100 120 current-limit voltage %/v 0.03 0.06 line regulation 1.2 v 4.85 5.06 5.25 5v output voltage (csl) v 1 5.5 nominal adjustable output voltage range % 2 load regulation units min typ max parameter 0 < (csh - csl) < 80mv, fb = 0v, 4.5v < v+ < 30v, includes line and load regulation v 3.20 3.34 3.46 3.3v output voltage (csl) 2.5 5.5 max1655 MAX1652/max1653/ max1654 2.43 2.50 2.57 MAX1652/max1653/ max1654 csh - csl = 0v, csl = fb, skip = 0v, 4.5v < v+ < 30v max1655 v 0.97 1.00 1.03 feedback voltage 3.3v and 5v step-down controllers flyback/pwm controller internal regulator and reference
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop _______________________________________________________________________________________ 3 note 1: since the reference uses vl as its supply, v+ line-regulation error is insignificant. note 2: at very low input voltages, quiescent supply current may increase due to excessive pnp base current in the vl linear regulator. this occurs if v+ falls below the preset vl regulation point (5v nominal). electrical characteristics (continued) (v+ = +15v, gnd = pgnd = 0v, sync = ref, i vl = i ref = 0a, t a = 0 c to +85 c, unless otherwise noted.) secfb, 0 or 4v shdn , 0 or 30v shdn , skip sync sync = 0 or 5v sync = ref guaranteed by design, not tested csh = csl = 5.5v v+ = 4.5v, csh = csl = 4.0v (note 2) sync = 0 or 5v falling edge 0 < i ref < 100 a sync = ref shdn = 0v, csl = 5.5v, csh = 5.5v, v+ = 0 or 30v, vl = 0v conditions 0.1 a 3.0 no external load (note 1) input current 2.0 v vl - 0.5 input high voltage % 98 99 97 98 dropout-mode maximum duty cycle khz 190 340 oscillator sync range ns 200 sync rise/fall time ns 200 sync low pulse width ns 200 sync high pulse width 125 150 175 khz 270 300 330 oscillator frequency 2.46 2.50 2.54 1 2 quiescent power consumption 1 8 dropout power consumption 5 15 v+ shutdown current v 2.0 2.4 reference fault lockout voltage mv 15 reference load regulation a 0.1 1 csl, csh shutdown leakage current units min typ max parameter shdn = 0v, v+ = 30v, csl = 0 or 5.5v fb = csh = csl = 5.5v, vl switched over to csl v+ off-state leakage current dl forced to 2v fb, fb = ref csh, csl, csh = csl 4v sync, skip a 1 dl sink/source current 0.1 70 1.0 shdn , skip sync 0.5 v 0.8 input low voltage dh forced to 2v, bst - lx = 4.5v a 1 dh sink/source current high or low, bst - lx = 4.5v high or low 1.5 5 dh on-resistance 1.5 5 dl on-resistance reference output voltage v oscillator and inputs/outputs 3 7 5 15 a a mw mw
v MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = +15v, gnd = pgnd = 0v, sync = ref, i vl = i ref = 0a, t a = -40 c to +85 c, unless otherwise noted.) (note 3) note 3: specifications from 0 c to -40 c are guaranteed by design, not production tested. 0 < (csh - csl) < 70mv, fb = vl, 4.5v < v+ < 30v, includes line and load regulation 0 < (csh - csl) < 70mv, fb = vl, 6v < v+ < 30v, includes line and load regulation conditions v 3.16 3.50 3.3v output voltage (csl) v 4.5 30 input supply range v 4.80 5.30 5v output voltage (csl) units min typ max parameter csh - csl, negative csh - csl, positive -40 -160 current-limit voltage v 0.96 1.04 feedback voltage 2.40 2.60 mv 70 130 fb = csh = csl = 5.5v, vl switched over to csl shdn = 0v, v+ = 30v, csl = 0 or 5.5v rising edge, hysteresis = 60mv no external load (note 1) 0 < i ref < 100 a a 15 v+ off-state leakage current a 10 v+ shutdown current v rising edge, hysteresis = 50mv shdn = 2v, 0 < i vl < 25ma, 5.5v < v+ < 30v 4.2 4.7 vl/csl switchover voltage v 2.43 2.57 reference output voltage falling edge, hysteresis = 22mv (MAX1652) falling edge, hysteresis = 22mv (max1654) mv 15 reference load regulation v 3.75 4.05 vl fault lockout voltage v 4.7 5.3 vl output voltage 2.40 2.60 v -0.08 0.08 secfb regulation setpoint sync = ref sync = 0 or 5v 97 khz 210 320 oscillator sync range khz sync = ref 120 180 oscillator frequency ns 250 sync high pulse width ns 250 sync low pulse width 250 350 mw 2 quiescent power consumption high or low, bst - lx = 4.5v high or low sync = 0 or 5v 5 dh on-resistance 5 dl on-resistance % 98 maximum duty cycle csh - csl = 0v, 5v < v+ < 30v, csl = fb, skip = 0v 6v < v+ < 30v %/v 0.06 line regulation 3.3v and 5v step-down controllers flyback/pwm controller internal regulator and reference oscillator and inputs/outputs MAX1652/max1653/ max1654 max1655
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop _______________________________________________________________________________________ 5 shdn dh +12v output +5v output input 6v to 30v bst lx dl pgnd csh csl ss ref sync gnd v+ vl fb secfb MAX1652 max1653 max1655 shdn dh +3.3v output input 4.5v to 30v bst lx dl pgnd csh csl ss ref sync gnd skip fb v+ vl t ypical operating cir cuits
__________________________________________ t ypical operating characteristics (circuit of figure 1, skip = gnd, t a = +25 c, unless otherwise noted.) 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (3.3v/1a circuit) 60 MAX1652 toc01 load current (a) efficiency (%) 70 80 90 v+ = 6v max1653 f = 300khz v+ = 28v v+ = 12v 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (3.3v/2a circuit) 60 MAX1652 toc02 load current (a) efficiency (%) 70 80 90 v+ = 6v v+ = 28v v+ = 12v max1653 f = 300khz 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (3.3v/3a circuit) 60 MAX1652 toc03 load current (a) efficiency (%) 70 80 90 v+ = 6v v+ = 28v v+ = 12v max1653 f = 300khz MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 6 _______________________________________________________________________________________ max1654 shdn dh -5v output +5v output input 6v to 30v bst lx dl pgnd csh csl ss ref from ref sync gnd v+ vl fb secfb t ypical operating cir cuits (continued)
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop _______________________________________________________________________________________ 7 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (5v/3a circuit) 60 MAX1652 toc04a load current (a) efficiency (%) 70 80 90 v+ = 28v v+ = 6v v+ = 12v max1653 f = 300khz ______________________________ ______ t ypical operating characteristics (continued) (circuit of figure 1, skip = gnd, t a = +25 c, unless otherwise noted.) 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (3.3v/5a circuit) 60 MAX1652 toc04 load current (a) efficiency (%) 70 80 90 v+ = 6v v+ = 28v v+ = 12v max1653 f = 300khz 0 10 5 20 15 25 30 0 10 15 5 20 25 30 pwm-mode supply current vs. input voltage (3.3v/3a circuit) MAX1652 toc07 input voltage (v) supply current (ma) max1653 skip = vl f = 300khz no load 100 50 0.001 0.1 1 0.01 10 efficiency vs. load current (1.8v/2.5a circuit) 60 MAX1652 toc05 load current (a) efficiency (%) 70 80 90 v+ = 6v v+ = 24v v+ = 12v max1655 f = 300khz 0.01 0 30 20 10 25 15 5 idle-mode supply current vs. input voltage (3.3v/3a circuit) 0.1 1 10 MAX1652 toc06 input voltage (v) supply current (ma) max1653 skip = 0 no load 0 4 2 6 8 10 0 10 15 5 20 25 30 shutdown supply current vs. input voltage MAX1652 toc08 input voltage (v) supply current ( m a) shdn = 0v 0 10 5 20 15 25 30 0 100 150 50 200 250 300 350 400 ref load-regulation error vs. ref load current MAX1652 toc010 load current (?) load regulation d v (mv) 0 300 900 600 1200 1500 0 10 15 5 20 25 30 MAX1652 maximum secondary output current vs. supply voltage MAX1652 toc12 supply voltage (v) maximum secondary current (ma) v sec > 12.75v, +5v output > 4.75v, circuit of figure 9 +5v load = 0a +5v load = 3a 0 10 5 20 15 25 50 45 40 35 30 0 20 30 10 40 50 60 70 80 vl load-regulation error vs. vl load current MAX1652 toc011 load current (ma) load regulation d v (mv)
output voltage load current 100mv/div, ac 2a/div time (10 m s) v in = 15v, 3.3v/3a circuit load-transient response MAX1652-16 output voltage lx voltage 10mv/div, ac 5v/div time (5 m s) v in = 5.1v, no load, 3.3v/3a circuit, set to 5v output (fb = vl) dropout waveforms MAX1652-15 MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 8 _______________________________________________________________________________________ output voltage lx voltage 10mv/div, ac 5v/div time (1 m s) v in = 6v, 3.3v/3a circuit pulse-width-modulation mode waveforms MAX1652-13 output voltage lx voltage 50mv/div, ac 5v/div time (2.5 m s) i load = 300ma, v in = 10v, 3.3v/3a circuit idle-mode waveforms MAX1652-14 t ypical operating characteristics (continued) (circuit of figure 1, skip = gnd, t a = +25 c, unless otherwise noted.) 0 0.01 10 1 0.1 dropout voltage vs. load current (3.3v/3a circuit) 100 300 400 200 500 MAX1652 toc09 load current (a) dropout voltage (mv) output set for 5v (fb = v l ) v out > 4.85v f = 150khz f = 300khz
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop _______________________________________________________________________________________ 9 pin description dual mode is a trademark of maxim integrated products. skip (max1653/ max1655) disables pulse-skipping mode when high. connect to gnd for normal use. don? leave skip unconnected. with skip grounded, the device will automatically change from pulse-skipping operation to full pwm opera - tion when the load current exceeds approximately 30% of maximum (table 3). 16 dh high-side gate-drive output. normally drives the main buck switch. dh is a floating driver output that swings from lx to bst, riding on the lx switching-node voltage. 15 lx switching node (inductor) connection. can swing 2v below ground without hazard. 14 bst boost capacitor connection for high-side gate drive (0.1 f) 13 dl low-side gate-drive output. normally drives the synchronous-rectifier mosfet. swings from 0v to vl. name function 1 ss soft-start timing capacitor connection. ramp time to full current limit is approximately 1ms/nf. 2 secfb (MAX1652/ max1654) secondary winding feedback input. normally connected to a resistor divider from an auxiliary output. don? leave secfb unconnected. MAX1652: secfb regulates at vsecfb = 2.50v. tie to vl if not used. max1654: secfb regulates at vsecfb = 0v. tie to a negative voltage through a high-value current- limiting resistor (i max = 100 a) if not used. pin 3 ref reference voltage output. bypass to gnd with 0.33 f minimum. 7 fb feedback input. regulates at the feedback voltage in adjustable mode. fb is a dual mode tm input that also selects the fixed output voltage settings as follows: connect to gnd for 3.3v operation. connect to vl for 5v operation. connect fb to a resistor divider for adjustable mode. fb can be driven with +5v cmos logic in order to change the output voltage under system control. 6 shdn shutdown control input, active low. logic threshold is set at approximately 1v (v th of an internal n-channel mosfet). tie shdn to v+ for automatic start-up. 5 sync oscillator synchronization and frequency select. tie to gnd or vl for 150khz operation; tie to ref for 300khz operation. a high-to-low transition begins a new cycle. drive sync with 0 to 5v logic levels (see the electrical characteristics table for v ih and v il specifications). sync capture range is 190khz to 340khz. 4 gnd low-noise analog ground and feedback reference point 12 pgnd power ground 11 vl 5v internal linear-regulator output. vl is also the supply voltage rail for the chip. vl is switched to the out - put voltage via csl (v csl > 4.5v) for automatic bootstrapping. bypass to gnd with 4.7 f. vl can supply up to 5ma for external loads. 10 v+ battery voltage input (4.5v to 30v). bypass v+ to pgnd close to the ic with a 0.1 f capacitor. connects to a linear regulator that powers vl. 9 csl current-sense input, low side. also serves as the feedback input in fixed-output modes. 8 csh current-sense input, high side. current-limit level is 100mv referred to csl.
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 10 ______________________________________________________________________________________ standar d application cir cuits it? easy to adapt the basic max1653 single-output 3.3v buck converter (figure 1) to meet a wide range of appli - cations with inputs up to 30v (limited by choice of exter - nal mosfet). simply substitute the appropriate components from table 1 (candidate suppliers are pro - vided in table 2). these circuits represent a good set of trade-offs among cost, size, and efficiency while staying within the worst-case specification limits for stress-relat - ed parameters such as capacitor ripple current. don? change the frequency of these circuits without first recalculating component values (particularly induc - tance value at maximum battery voltage). for a discussion of dual-output circuits using the MAX1652 and max1654, see figure 9 and the secondary feedback-regulation loop section. detailed description the MAX1652 family are bicmos, switch-mode power- supply controllers designed primarily for buck-topology regulators in battery-powered applications where high efficiency and low quiescent supply current are critical. the parts also work well in other topologies such as boost, inverting, and cuk due to the flexibility of their floating high-speed gate driver. light-load efficiency is enhanced by automatic idle-mode operation? vari - able-frequency pulse-skipping mode that reduces losses due to mosfet gate charge. the step-down power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output filter. the out - put voltage is the average of the ac voltage at the switching node, which is adjusted and regulated by changing the duty cycle of the mosfet switches. the gate-drive signal to the n-channel high-side mosfet must exceed the battery voltage and is provided by a flying capacitor boost circuit that uses a 100nf capaci - tor connected to bst. max1653 csl csh vl sync fb v+ 10 11 5 7 14 q1 q2 16 15 13 d2 cmpsh-3 j1 150khz/300khz jumper note: keep current-sense lines short and close together. see figure 8. d1 12 8 9 ref 3 gnd 4 +5v at 5ma +3.3v output gnd out bst dh lx dl 2 1 low-noise control pgnd skip ss 6 on/off control shdn input ref output +2.5v at 100 m a c5 0.33 m f c4 4.7 m f c7 0.1 m f c6 0.01 m f (optional) c1 c2 c3 0.1 m f r1 l1 figure 1. standard 3.3v application circuit (see table 1 for component values)
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 11 table 1. component selection for standard applications component 3.3v at 1a 3.3v at 2a 5v/3.3v at 3a 3.3v at 5a 1.8v at 2.5a frequency 300khz 300khz 300khz 300khz 150khz q1 high-side mosfet international rectifier 1/2 irf7101 international rectifier 1/2 irf7303 or fairchild semiconductor 1/2 nds8936 international rectifier irf7403 or fairchild semiconductor nds 8410a fairchild semiconductor fds6680 i nternational rectifier 1/2 irf7303 or fairchild semiconductor 1/2 nds8936 q2 low-side mosfet international rectifier 1/2 irf7101 international rectifier 1/2 irf7303 or fairchild semiconductor 1/2 nds8936 international rectifier irf7403 or fairchild semiconductor nds 8410a fairchild semiconductor fds6680 international rectifier 1/2 irf7303 or fairchild semiconductor 1/2 nds8936 c1 input capacitor 10 f, 35v avx tpsd106m035r0300 22 f, 35v avx tpse226m035r0300 (2) 22 f, 35v avx tpse226m035r0300 (3) 22 f, 35v avx tpse226m035r0300 10 f, 25v ceramic taiyo yuden tmk325f106z c2 output capacitor 100 f, 6.3v avx tpsc107m006r 220 f, 10v avx tpse227m010r0100 or sprague 594d227x001002t 470 f, 6v (for 3.3v) kemet t510x477m006as or (2) 220 f, 10v (for 5v) avx tpse227m010r011 (3) 330 f, 10v sprague 594d337x0010r2t or (2) 470 f, 6v kemet t510x477m006as 470 f, 4v sprague 594d477x0004r2t or 470 f, 6v kemet t510x477m006as d1 rectifier 1n5819 or motorola mbr0520l 1n5819 or motorola mbrs130lt3 1n5819 or motorola mbrs130lt3 1n5821 or motorola mbrs340t3 1n5817 or motorola mbrs130lt3 r1 sense resistor 70m dale wsl-1206-r070f or irc lr2010-01-r070 33m dale wsl-2010-r033f or irc lr2010-01-r033 25m dale wsl-2010-r025f or irc lr2010-01-r025 12m dale wsl-2512-r012f 30m dale wsl-2010-r030f or irc lr2010-01-r030 l1 inductor 33 h sumida cdr74b-330 15 h sumida cdr105b-150 10 h sumida cdrh125-100 4.7 h sumida cdrh127-4r7 15 h sumida cdrh125-150 table 2. component suppliers * distributor [1] 602-994-6430 602-303-5454 motorola [1] 408-986-1442 408-986-0424 kemet [1] 512-992-3377 512-992-7900 irc [1] 408-721-1635 408-822-2181 fairchild [1] 605-665-1627 605-668-4131 dale [1] 561-241-9339 561-241-7876 coiltronics [1] 847-639-1469 847-639-6400 coilcraft [1] 516-435-1824 516-435-1110 central semiconductor [1] 803-626-3123 803-946-0690 avx factory fax [country code] usa phone manufacturer input range 4.75v to 28v 4.75v to 28v 4.75v to 28v 4.75v to 28v 4.75v to 22v [1] 408-573-4159 408-573-4150 taiyo yuden [81] 3-3607-5144 847-956-0666 sumida [1] 603-224-1430 603-224-1961 sprague [1] 408-970-3950 408-988-8000 800-554-5565 siliconix [81] 7-2070-1174 619-661-6835 sanyo [81] 3-3494-7414 805-867-2555* niec [1] 814-238-0490 814-237-1431 800-831-9172 murata factory fax [country code] usa phone manufacturer [1] 702-831-3521 702-831-0140 transpower technologies [1] 714-960-6492 714-969-2491 matsuo [1] 310-322-3332 310-322-3331 international rectifier [1] 847-390-4405 847-390-4461 tdk
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 12 ______________________________________________________________________________________ the MAX1652?ax1655 contain nine major circuit blocks, which are shown in figure 2: pwm controller blocks: multi-input pwm comparator current-sense circuit pwm logic block dual-mode internal feedback mux gate-driver outputs secondary feedback comparator bias generator blocks: +5v linear regulator automatic bootstrap switchover circuit +2.50v reference these internal ic blocks aren? powered directly from the battery. instead, a +5v linear regulator steps down the battery voltage to supply both the ic internal rail (vl pin) as well as the gate drivers. the synchronous- switch gate driver is directly powered from +5v vl, while the high-side-switch gate driver is indirectly pow - ered from vl via an external diode-capacitor boost cir - cuit. an automatic bootstrap circuit turns off the +5v linear regulator and powers the ic from its output volt - age if the output is above 4.5v. pwm controller block the heart of the current-mode pwm controller is a multi-input open-loop comparator that sums three sig - nals: output voltage error signal with respect to the ref - erence voltage, current-sense signal, and slope compensation ramp (figure 3). the pwm controller is a direct summing type, lacking a traditional error amplifi - er and the phase shift associated with it. this direct- summing configuration approaches the ideal of cycle-by-cycle control over the output voltage. under heavy loads, the controller operates in full pwm mode. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a peri - od determined by the duty factor (approximately v out /v in ). as the high-side switch turns off, the syn - chronous rectifier latch is set. 60ns later the low-side switch turns on, and stays on until the beginning of the next clock cycle (in continuous mode) or until the inductor current crosses zero (in discontinuous mode). under fault conditions where the inductor current exceeds the 100mv current-limit threshold, the high- side latch resets and the high-side switch turns off. if the load is light in idle mode ( skip = low), the induc - tor current does not exceed the 25mv threshold set by the idle mode comparator. when this occurs, the con - troller skips most of the oscillator pulses in order to reduce the switching frequency and cut back gate- charge losses. the oscillator is effectively gated off at light loads because the idle mode comparator immedi - ately resets the high-side latch at the beginning of each cycle, unless the feedback signal falls below the refer - ence voltage level. when in pwm mode, the controller operates as a fixed- frequency current-mode controller where the duty ratio is set by the input/output voltage ratio. the current- mode feedback system regulates the peak inductor current as a function of the output voltage error signal. since the average inductor current is nearly the same as the peak current, the circuit acts as a switch-mode transconductance amplifier and pushes the second out- put lc filter pole, normally found in a duty-factor- controlled (voltage-mode) pwm, to a higher frequency. to preserve inner-loop stability and eliminate regenera - tive inductor current ?taircasing,?a slope-compensa - tion ramp is summed into the main pwm comparator to reduce the apparent duty factor to less than 50%. the relative gains of the voltage- and current-sense inputs are weighted by the values of current sources that bias three differential input stages in the main pwm comparator (figure 4). the relative gain of the voltage comparator to the current comparator is internally fixed at k = 2:1. the resulting loop gain (which is relatively low) determines the 2% typical load regulation error. the low loop-gain value helps reduce output filter capacitor size and cost by shifting the unity-gain crossover to a lower frequency. the output filter capacitor c2 sets a dominant pole in the feedback loop. this pole must roll off the loop gain to unity before the zero introduced by the output capacitor? parasitic resistance (esr) is encountered (see design procedure section). a 12khz pole-zero cancellation filter provides additional rolloff above the unity-gain crossover. this internal 12khz lowpass com - pensation filter cancels the zero due to the filter capaci - tor? esr. the 12khz filter is included in the loop in both fixed- and adjustable-output modes. synchronous-rectifier driver (dl pin) synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky diode with a low-resistance mosfet switch. the synchronous rec - tifier also ensures proper start-up of the boost-gate driv- er circuit. if you must omit the synchronous power mosfet for cost or other reasons, replace it with a small-signal mosfet such as a 2n7002. if the circuit is operating in continuous-conduction mode, the dl drive waveform is simply the complement of the dh high-side drive waveform (with controlled dead time to prevent cross-conduction or ?hoot - through? .
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 13 MAX1652 max1653 max1654 max1655 1v csl csh ref gnd 4v fb adj fb 5v fb 3.3v fb sync lpf 12khz pwm comparator out v+ battery voltage 4.5v vl to csl +5v at 5ma bst dh lx dl pgnd secfb main output auxiliary output shdn pwm logic shdn ss on/off +2.50v at 100 m a +5v linear regulator +2.50v ref figure 2. MAX1652?ax1655 functional diagram
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 14 ______________________________________________________________________________________ shoot- through control r q 25mv r q level shift 1 m s single-shot main pwm comparator osc level shift current limit vl 24r 1r 2.5v 4 m a synchronous- rectifier control 2.5v (1v, max1655) ss shdn -100mv (note 1) comparator csh csl from feedback divider bst dh lx vl dl pgnd s s slope comp idle mode comparator n skip (max1653/ max1655 only) ref (MAX1652) gnd (max1654) MAX1652, max1654 only secfb note 1: comparator input polarities are reversed for the max1654. figure 3. pwm controller detailed block diagram
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 15 in discontinuous (light-load) mode, the synchronous switch is turned off as the inductor current falls through zero. the synchronous rectifier works under all operat - ing conditions, including idle mode. the synchronous- switch timing is further controlled by the secondary feedback (secfb) signal in order to improve multiple- output cross-regulation (see secondary feedback- regulation loop section). internal vl and ref supplies an internal regulator produces the 5v supply (vl) that powers the pwm controller, logic, reference, and other blocks. this +5v low-dropout linear regulator can sup - ply up to 5ma for external loads, with a reserve of 20ma for gate-drive power. bypass vl to gnd with 4.7 f. important : vl must not be allowed to exceed 5.5v. measure vl with the main output fully loaded. if vl is being pumped up above 5.5v, the probable cause is either excessive boost-diode capacitance or excessive ripple at v+. use only small-signal diodes for d2 (10ma to 100ma schottky or 1n4148 are preferred) and bypass v+ to pgnd with 0.1 f directly at the package pins. the 2.5v reference (ref) is accurate to 1.6% over temperature, making ref useful as a precision system reference. bypass ref to gnd with 0.33 f minimum. ref can supply up to 1ma for external loads. however, if tight-accuracy specs for either v out or ref are essential, avoid loading ref with more than 100 a. loading ref reduces the main output voltage slightly, according to the reference-voltage load regulation error. in max1654 applications, ensure that the secfb divider doesn? load ref heavily. when the main output voltage is above 4.5v, an internal p-channel mosfet switch connects csl to vl while simultaneously shutting down the vl linear regulator. this action bootstraps the ic, powering the internal cir - cuitry from the output voltage, rather than through a lin - ear regulator from the battery. bootstrapping reduces power dissipation caused by gate-charge and quies - cent losses by providing that power from a 90%-effi - cient switch-mode source, rather than from a less efficient linear regulator. it? often possible to achieve a bootstrap-like effect, even for circuits that are set to v out < 4.5v, by power - ing vl from an external-system +5v supply. to achieve this pseudo-bootstrap, add a schottky diode between the external +5v source and vl, with the cathode to the vl side. this circuit provides a 1% to 2% efficiency boost and also extends the minimum battery input to less than 4v. the external source must be in the range of 4.8v to 5.5v. boost high-side gate-driver supply (bst pin) gate-drive voltage for the high-side n-channel switch is generated by a flying-capacitor boost circuit as shown in figure 5. the capacitor is alternately charged from the vl supply and placed in parallel with the high-side mosfet? gate-source terminals. on start-up, the synchronous rectifier (low-side mos - fet) forces lx to 0v and charges the bst capacitor to 5v. on the second half-cycle, the pwm turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary enhancement voltage to turn on the high-side switch, fb ref csh csl slope compensation vl i1 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i2 i3 figure 4. main pwm comparator block diagram
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 16 ______________________________________________________________________________________ an action that ?oosts?the 5v gate-drive signal above the battery voltage. ringing seen at the high-side mosfet gate (dh) in discontinuous-conduction mode (light loads) is a natur - al operating condition caused by the residual energy in the tank circuit formed by the inductor and stray capac - itance at the switching node lx. the gate-driver nega - tive rail is referred to lx, so any ringing there is directly coupled to the gate-drive output. current-limiting and current-sense inputs (csh and csl) the current-limit circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl exceeds 100mv. this limiting is effective for both current flow directions, putting the threshold limit at 100mv. the tolerance on the positive current limit is 20%, so the external low-value sense resistor must be sized for 80mv/r1 to guarantee enough load capability, while components must be designed to withstand continuous current stresses of 120mv/r1. for breadboarding purposes or very-high-current appli - cations, it may be useful to wire the current-sense inputs with a twisted pair rather than pc traces. oscillator frequency and synchronization (sync pin) the sync input controls the oscillator frequency. connecting sync to gnd or to vl selects 150khz operation; connecting sync to ref selects 300khz. sync can also be used to synchronize with an external 5v cmos clock generator. sync has a guaranteed 190khz to 340khz capture range. 300khz operation optimizes the application circuit for component size and cost. 150khz operation provides increased efficiency and improved low-duty factor operation (see dropout operation section). dropout operation dropout (low input-output differential operation) is en- hanced by stretching the clock pulse width to increase the maximum duty factor. the algorithm follows: if the out - put voltage (v out ) drops out of regulation without the current limit having been reached, the controller skips an off-time period (extending the on-time). at the end of the cycle, if the output is still out of regulation, another off-time period is skipped. this action can continue until three off- time periods are skipped, effectively dividing the clock frequency by as much as four. the typical pwm minimum off-time is 300ns, regardless of the operating frequency. lowering the operating fre - quency raises the maximum duty factor above 98%. low-noise mode ( skip pin) the low-noise mode ( skip = high) is useful for minimiz - ing rf and audio interference in noise-sensitive appli - cations such as audio-equipped systems, cellular phones, rf communicating computers, and electro - magnetic pen-entry systems. see the summary of oper - ating modes in table 3. skip can be driven from an external logic signal. the max1653 and max1655 can reduce interference due to switching noise by ensuring a constant switch - ing frequency regardless of load and line conditions, thus concentrating the emissions at a known frequency outside the system audio or if bands. choose an oscil - lator frequency where harmonics of the switching fre - quency don? overlap a sensitive frequency band. if necessary, synchronize the oscillator to a tight-toler - ance external clock generator. the low-noise mode ( skip = high) forces two changes upon the pwm controller. first, it ensures fixed-frequen - cy operation by disabling the minimum-current com - parator and ensuring that the pwm latch is set at the beginning of each cycle, even if the output is in regula - tion. second, it ensures continuous inductor current MAX1652 max1653 max1654 max1655 bst vl +5v vl supply battery input vl vl dh lx dl pwm level translator figure 5. boost supply for gate drivers
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 17 flow, and thereby suppresses discontinuous-mode inductor ringing by changing the reverse current-limit detection threshold from 0 to -100mv, allowing the inductor current to reverse at very light loads. in most applications, skip should be tied to gnd in order to minimize quiescent supply current. supply cur - rent with skip high is typically 10ma to 20ma, depend - ing on external mosfet gate capacitance and switching losses. forced continuous conduction via skip can improve cross regulation of transformer-coupled multiple-output supplies. this second function of the skip pin produces a result that is similar to the method of adding sec - ondary regulation via the secfb feedback pin, but with much higher quiescent supply current. still, improving cross regulation by enabling skip instead of building in secfb feedback can be useful in noise-sensitive appli - cations, since secfb and skip are mutually exclusive pins/functions in the MAX1652 family. adjustable-output feedback (dual-mode fb pin) the MAX1652?ax1655 family has both fixed and adjustable output voltage modes. for fixed mode, con - nect fb to gnd for a 3.3v output and to v l for a 5v out - put. adjusting the main output voltage with external resistors is easy for any of the devices in this family, via the circuit of figure 6. the feedback voltage is nominal - ly 2.5 for all family members except the max1655, which has a nominal fb voltage of 1v. the output volt - age (given by the formula in figure 6) should be set approximately 2% high in order to make up for the MAX1652? load-regulation error. for example, if designing for a 3.0v output, use a resistor ratio that results in a nominal output voltage of 3.06v. this slight offsetting gives the best possible accuracy. recommended normal values for r5 range from 5k to 100k . remote sensing of the output voltage, while not possi - ble in fixed-output mode due to the combined nature of the voltage- and current-sense input (csl), is easy to achieve in adjustable mode by using the top of the external resistor divider as the remote sense point. duty-factor limitations for low v out /v in ratios the MAX1652/max1653/max1654? output voltage is adjustable down to 2.5v and the max1655? output is adjustable as low as 1v. however, the minimum duty factor may limit the choice of operating frequency, high input voltage, and low output voltage. MAX1652 max1653 max1654 max1655 csl csh gnd fb r4 r5 main output remote sense lines dh dl v out where v ref (nominal) = 2.5v (MAX1652?ax1654) = 1.0v (max1655) = v ref ( 1 + ) r4 r5 v+ figure 6. adjusting the main output voltage shdn skip load current mode name description low x x shutdown all circuit blocks turned off; supply current = 3 a typ high low low, <10% idle pulse-skipping; supply current = 300 a typ at v in = 10v; discontinuous inductor current high low medium, <30% idle pulse-skipping; continuous inductor current high low high, >30% pwm constant-frequency pwm; continuous inductor current high high x low noise* (pwm) constant-frequency pwm regardless of load; continuous inductor current even at no load table 3. operating-mode truth table * MAX1652/max1654 have no skip pin and therefore can? go into low-noise mode. x = don? care
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 18 ______________________________________________________________________________________ with high input voltages, the required duty factor is approximately (v out + v q2 )/ v in , where v q2 is the volt - age drop across the synchronous rectifier. the MAX1652? minimum duty factor is determined by delays through the feedback network, error comparator, internal logic gate drivers, and the external mosfets, which typically total 400ns. this delay is about 12% of the switching period at 300khz and 6% at 150khz, limit - ing the typical minimum duty factor to these values. even if the circuit can not attain the required duty factor dictated by the input and output voltages, the output voltage will remain in regulation. however, there may be intermittent or continuous half-frequency operation. this can cause a factor-of-two increase in output voltage rip - ple and current ripple, which will increase noise and reduce efficiency. choose 150khz operation for high- input-voltage/low-output-voltage circuits. secondary feedback-regulation loop (secfb pin) a flyback winding control loop regulates a secondary winding output (MAX1652/max1654 only), improving cross-regulation when the primary is lightly loaded or when there is a low input-output differential voltage. if secfb crosses its regulation threshold, a 1 s one- s hot is triggered that extends the low-side switch? on-time beyond the point where the inductor current crosses zero (in dis continuous mode). this causes the inductor (primary) current to reverse, which in turn pulls current out of the output filter capacitor and causes the flyback transformer to operate in the forward mode. the low impedance presented by the transformer secondary in the forward mode dumps current into the secondary output, charging up the secondary capacitor and bring - ing secfb back into regulation. the secfb feedback loop does not improve secondary output accuracy in normal flyback mode, where the main (primary) output is heavily loaded. in this mode, secondary output accura - cy is determined (as usual) by the secondary rectifier drop, turns ratio, and accuracy of the main output volt - age. hence, a linear post-regulator may still be needed in order to meet tight output accuracy specifications. the secondary output voltage-regulation point is deter - mined by an external resistor-divider at secfb. for neg - ative output voltages, the secfb comparator is referenced to gnd (max1654); for positive output volt - ages, secfb regulates at the 2.50v reference (MAX1652). as a result, output resistor-divider connec - tions and design equations for the two device types dif - fer slightly (figure 7). ordinarily, the secondary regulation po int is set 5% to 10% below the voltage nor - mally produced by the flyback effect. for example, if the max1654 negative secondary output main output dh v+ secfb r3 r2 1-shot trig dl 0.33 m f ref MAX1652 positive secondary output main output dh v+ secfb 2.5v ref r3 r2 1-shot trig dl +v trip where v ref (nominal) = 2.5v = v ref ( 1 + ) r2 r3 -v trip r3 = 100k w (recommended) = -v ref ( ) r2 r3 figure 7. secondary-output feedback dividers
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 19 output voltage as determined by the turns ratio is +15v, the feedback resistor ratio should be set to produce about +13.5v; otherwise, the secfb one-shot might be triggered unintentionally, causing an unnecessary increase in supply current and output noise. in negative- output (max1654) applications, the resistor-divider acts as a load on the internal reference, which in turn can cause errors at the main output. avoid overloading ref (see the reference load-regulation error vs. load current graph in the typical operating characteristics ). 100k is a good value for r3 in max1654 circuits. output current on secondary winding applications is limited at low input voltages. see the MAX1652 maximum secondary output current vs. supply voltage graph in the typical operating characteristics for data from the application circuit of figure 8. soft-start circuit (ss) soft-start allows a gradual increase of the internal cur - rent-limit level at start-up for the purpose of reducing input surge currents, and perhaps for power-supply sequencing. in shutdown mode, the soft-start circuit holds the ss capacitor discharged to ground. when shdn goes high, a 4 a current source charges the ss capacitor up to 3.2v. the resulting linear ramp wave - form causes the internal current-limit level to increase proportionally from 0 to 100mv. the main output capaci - tor thus charges up relatively slowly, depending on the ss capacitor value. the exact time of the output rise depends on output capacitance and load current and is typically 1ms per nanofarad of soft-start capacitance. with no ss capacitor connected, maximum current limit is reached within 10 s. shutdown shutdown mode ( shdn = 0v) reduces the v+ supply current to typically 3 a. in this mode, the reference and vl are inactive. shdn is a logic-level input, but it can be safely driven to the full v+ range. connect shdn to v+ for automatic start-up. do not allow slow transitions (slower than 0.02v/ s) on shdn . MAX1652 fb gnd ref sync secfb vl 10 2 11 7 3 5 14 si9410 si9410 d2 ec11fs1 t1 = transpower tti5870 * = optional, may not be needed 16 15 13 d1 cmpsh -3a 1n5819 12 8 9 v in (6.5v to 18v) +15v at 250ma +5v at 3a 6 on/off 1 csl csh bst v+ dh lx dl pgnd shdn ss 0.33 m f c2 4.7 m f c3 15 m f 2.5v 220 m f 10v 220 m f 10v 0.1 m f 22 m f, 35v 22 m f, 35v 0.01 m f 20m w 22 w * 4700pf* t1 15 m h 2.2:1 49.9k, 1% 210k, 1% 0.01 m f (optional) 18v 1/4 w c2 4.7 m f 4 figure 8. 5v/15v dual-output application circuit (MAX1652)
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 20 ______________________________________________________________________________________ __________________design pr ocedur e the predesigned standard application circuits (figure 1 and table 1) contain ready-to-use solutions for com - mon applications. use the following design procedure to optimize the basic schematic for different voltage or current requirements. before beginning a design, firmly establish the following: v in(max) , the maximum input (battery) voltage. this value should include the worst-case conditions, such as no-load operation when a battery charger or ac adapter is connected but no battery is installed. v in(max) must not exceed 30v. this 30v upper limit is determined by the breakdown voltage of the bst float - ing gate driver to gnd (36v absolute maximum). v in(min) , the minimum input (battery) voltage. this should be at full-load under the lowest battery condi - tions. if v in(min) is less than 4.5v, a special circuit must be used to externally hold up vl above 4.8v. if the min - imum input-output difference is less than 1v, the filter capacitance required to maintain good ac load regula - tion increases. inductor value the exact inductor value isn? critical and can be adjusted freely in order to make trade-offs among size, cost, and efficiency. although lower inductor values will minimize size and cost, they will also reduce efficiency due to higher peak currents. to permit use of the physi - cally smallest inductor, lower the inductance until the circuit is operating at the border between continuous and discontinuous modes. reducing the inductor value even further, below this crossover point, results in dis - continuous-conduction operation even at full load. this helps reduce output filter capacitance requirements but causes the core energy storage requirements to increase again. on the other hand, higher inductor val - ues will increase efficiency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower ac current levels. also, high induc - tor values affect load-transient response; see the v sag equation in the low-voltage operation section. the following equations are given for continuous-conduc - tion operation since the MAX1652 family is mainly intend - ed for high-efficiency, battery-powered applications. see appendix a in maxim? battery management and dc-dc converter circuit collection for crossover point and dis - continuous-mode equations. discontinuous conduction doesn? affect normal idle mode operation. three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant lir, which is the ratio of inductor peak-to-peak ac current to dc load current. a higher value of lir allows smaller inductance, but results in higher losses and ripple. a good compromise between size and loss - es is found at a 30% ripple current to load current ratio (lir = 0.3), which corresponds to a peak inductor cur - rent 1.15 times higher than the dc load current. v out (v in(max) - v out ) l = v in(max) x f x i out x lir where: f = switching frequency, normally 150khz or 300khz i out = maximum dc load current lir = ratio of ac to dc inductor current, typically 0.3 the peak inductor current at full load is 1.15 x i out if the above equation is used; otherwise, the peak current can be calculated by: the inductor? dc resistance is a key parameter for effi - ciency performance and must be ruthlessly minimized, preferably to less than 25m at i out = 3a. if a stan - dard off-the-shelf inductor is not available, choose a core with an li 2 rating greater than l x i peak 2 and wind it with the largest diameter wire that fits the winding area. for 300khz applications, ferrite core material is strongly preferred; for 150khz applications, kool-mu (aluminum alloy) and even powdered iron can be acceptable. if light-load efficiency is unimportant (in desktop 5v-to-3v applications, for example) then low- permeability iron-powder cores may be acceptable, even at 300khz. for high-current applications, shielded core geometries (such as toroidal or pot core) help keep noise, emi, and switching-waveform jitter low. current-sense resistor value the current-sense resistor value is calculated accord - ing to the worst-case, low-current-limit threshold voltage (from the electrical characteristics table) and the peak inductor current. the continuous-mode peak inductor- current calculations that follow are also useful for sizing the switches and specifying the inductor-current satu - ration ratings. in order to simplify the calculation, i load may be used in place of i peak if the inductor value has been set for lir = 0.3 or less (high inductor values) and 300khz operation is selected. low-inductance resistors, such as surface-mount metal-film resistors, are preferred. 80mv r sense = i peak i i x f x l x v peak load in max = + ( ) v (v - v ) out in(max) out 2
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 21 input capacitor value place a small ceramic capacitor (0.1 f) between v+ and gnd, close to the device. also, connect a low-esr bulk capacitor directly to the drain of the high-side mosfet. select the bulk input filter capacitor according to input ripple-current requirements and voltage rating, rather than capacitor value. electrolytic capacitors that have low enough effective series resistance (esr) to meet the ripple-current requirement invariably have more than adequate capacitance values. ceramic capacitors or low-esr aluminum-electrolytic capacitors such as sanyo os-con or nichicon pl are preferred. tantalum types are also acceptable but may be less tolerant of high input surge currents. rms input ripple current is deter - mined by the input voltage and load current, with the worst possible case occurring at v in = 2 x v out : output filter capacitor value the output filter capacitor values are determined by the esr, capacitance, and voltage rating requirements. electrolytic and tantalum capacitors are generally cho - sen by voltage rating and esr specifications, as they will generally have more output capacitance than is required for ac stability. use only specialized low-esr capacitors intended for switching-regulator applications, such as avx tps, sprague 595d, sanyo os-con, or nichicon pl series. to ensure stability, the capacitor must meet both minimum capacitance and maximum esr values as given in the following equations: v ref (1 + v out / v in(min) ) c out > v out x r sense x f r sense x v out r esr < v ref (can be multiplied by 1.5, see note below) these equations are ?orst-case?with 45 degrees of phase margin to ensure jitter-free fixed-frequency opera - tion and provide a nicely damped output response for zero to full-load step changes. some cost-conscious designers may wish to bend these rules by using less expensive (lower quality) capacitors, particularly if the load lacks large step changes. this practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. there is no well-defined boundary between stable and unstable operation. as phase margin is reduced, the first symptom is a bit of timing jitter, which shows up as blurred edges in the switching waveforms where the scope won? quite sync up. technically speaking, this (usually) harmless jitter is unstable operation, since the switching frequency is now nonconstant. as the capac - itor quality is reduced, the jitter becomes more pro - nounced and the load-transient output voltage waveform starts looking ragged at the edges. eventually, the load-transient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage tolerance. note that even with zero phase margin and gross instability present, the output voltage noise never gets much worse than i peak x r esr (under constant loads, at least). note : designers of rf communicators or other noise- sensitive analog equipment should be conservative and stick to the esr guidelines. designers of notebook computers and similar commercial-temperature-range digital systems can multiply the r esr value by a factor of 1.5 without hurting stability or transient response. the output voltage ripple is usually dominated by the esr of the filter capacitor and can be approximated as i ripple x r esr . there is also a capacitive term, so the full equation for ripple in the continuous mode is v noise(p-p) = i ripple x [r esr + 1 / (8 x f x c out )]. in idle mode, the inductor current becomes discontinuous with high peaks and widely spaced pulses, so the noise can actually be higher at light load compared to full load. in idle mode, the output ripple can be calculated as: 0.025 x r esr v noise(p-p) = + r sense (0.025) 2 x l x [1 / v out + 1 / (v in - v out )] (r sense ) 2 x c out transformer design (MAX1652/max1654 only) buck-plus-flyback applications, sometimes called ?ou - pled-inductor?topologies, use a transformer to generate multiple output voltages. the basic electrical design is a simple task of calculating turns ratios and adding the power delivered to the secondary in order to calculate the current-sense resistor and primary inductance. however, extremes of low input-output differentials, widely different output loading levels, and high turns ratios can compli - cate the design due to parasitic transformer parameters such as interwinding capacitance, secondary resistance, and leakage inductance. for examples of what is possi - ble with real-world transformers, see the graphs of maximum secondary current vs. input voltage in the typical operating characteristics. i i x v v i i when v is x v rms load out vin vout in rms load in out / ( ) = = - 2 2
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 22 ______________________________________________________________________________________ power from the main and secondary outputs is lumped together to obtain an equivalent current referred to the main output voltage (see inductor value section for def - initions of parameters). set the value of the current- sense resistor at 80mv / i total . p total = the sum of the output power from all outputs i total = p total / v out = the equivalent output current referred to v out v out (v in(max) - v out ) l(primary) = v in(max) x f x i total x lir v sec + v fwd turns ratio n = v out(min) + v rect + v sense where: v sec is the minimum required rectified secondary-output voltage v fwd is the forward drop across the secondary rectifier v out(min) is the minimum value of the main output voltage (from the electrical characteristics ) v rect is the on-state voltage drop across the synchronous-rectifier mosfet v sense is the voltage drop across the sense resistor in positive-output (MAX1652) applications, the trans - former secondary return is often referred to the main output voltage rather than to ground in order to reduce the needed turns ratio. in this case, the main output voltage must first be subtracted from the secondary voltage to obtain v sec . ______ selecting other components mosfet switches the two high-current n-channel mosfets must be logic-level types with guaranteed on-resistance specifi - cations at v gs = 4.5v. lower gate threshold specs are better (i.e., 2v max rather than 3v max). drain-source breakdown voltage ratings must at least equal the max - imum input voltage, preferably with a 20% derating factor. the best mosfets will have the lowest on-resis - tance per nanocoulomb of gate charge. multiplying r ds(on) x q g provides a meaningful figure by which to compare various mosfets. newer mosfet process technologies with dense cell structures generally give the best performance. the internal gate drivers can tol - erate more than 100nc total gate charge, but 70nc is a more practical upper limit to maintain best switching times. i n high-current applications, mosfet package power dissipation often becomes a dominant design factor. i 2 r losses are distributed between q1 and q2 accord - ing to duty factor (see the equations below). switching losses affect the upper mosfet only, since the schottky rectifier clamps the switching node before the synchronous rectifier turns on. gate-charge losses are dissipated by the driver and don? heat the mosfet. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. the worst-case dissi - pation for the high-side mosfet occurs at the minimum battery voltage, and the worst-case for the low-side mosfet occurs at the maximum battery voltage. pd (upper fet) = i load 2 x r ds(on) x duty v in x c rss + v in x i load x f x ( ?+20ns ) i gate pd (lower fet) = i load 2 x r ds(on) x (1 - duty) duty = (v out + v q2 ) / (v in - v q1 + v q2 ) where the on-state voltage drop v q_ = i load x r ds(on) c rss = mosfet reverse transfer capacitance i gate = dh driver peak output current capability (1a typically) 20ns = dh driver inherent rise/fall time under output short circuit, the synchronous-rectifier mosfet suffers extra stress and may need to be over- sized if a continuous dc short circuit must be tolerated. during short circuit, q2? duty factor can increase to greater than 0.9 according to: q2 duty (short circuit) = 1 - [v q2 / (v in(max) - v q1 + v q2 )] where the on-state voltage drop v q = (120mv / r sense ) x r ds(on). rectifier diode d1 rectifier d1 is a clamp that catches the negative induc - tor swing during the 60ns dead time between turning off the high-side mosfet and turning on the low-side. d1 must be a schottky type in order to prevent the lossy parasitic mosfet body diode from conducting. it is acceptable to omit d1 and let the body diode clamp the negative inductor swing, but efficiency will drop one or two percent as a result. use an mbr0530 (500ma rated) type for loads up to 1.5a, a 1n5819 type for loads up to 3a, or a 1n5822 type for loads up to 10a. d1? rated reverse breakdown voltage must be at least equal to the maximum input voltage, preferably with a 20% derating factor.
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 23 boost-supply diode d2 a 10ma to 100ma schottky diode or signal diode such as a 1n4148 works well for d2 in most applications. if the input voltage can go below 6v, use a schottky diode for slightly improved efficiency and dropout char - acteristics. don? use large power diodes such as 1n5817 or 1n4001, since high junction capacitance can cause vl to be pumped up to excessive voltages. rectifier diode d3 (transformer secondary diode) the secondary diode in coupled-inductor applications must withstand high flyback voltages greater than 60v, which usually rules out most schottky rectifiers. common silicon rectifiers such as the 1n4001 are also prohibited, as they are far too slow. this often makes fast silicon rectifiers such as the murs120 the only choice. the flyback voltage across the rectifier is relat - ed to the v in -v out difference according to the trans - former turns ratio: v flyback = v sec + (v in - v out ) x n where: n is the transformer turns ratio sec/pri v sec is the maximum secondary dc output voltage v out is the primary (main) output voltage subtract the main output voltage (v out ) from v flyback in this equation if the secondary winding is returned to v out and not to ground. the diode reverse breakdown rating must also accommodate any ringing due to leak - age inductance. d3? current rating should be at least twice the dc load current on the secondary output. _____________low-v oltage operation low input voltages and low input-output differential volt - ages each require some extra care in the design. low absolute input voltages can cause the vl linear regula - tor to enter dropout, and eventually shut itself off. low input voltages relative to the output (low v in -v out differ - ential) can cause bad load regulation in multi-output fly - back applications. see transformer design section. finally, low v in -v out differentials can also cause the output voltage to sag when the load current changes abruptly. the amplitude of the sag is a function of induc - tor value and maximum duty factor (d max an electrical characteristics parameter, 98% guaranteed over tem - perature at f = 150khz) as follows: (i step ) 2 x l v sag = 2 x c out x (v in(min) x d max - v out ) the cure for low-voltage sag is to increase the value of the output capacitor. for example, at v in = 5.5v, v out = 5v, l = 10 h, f = 150khz, a total capacitance of 660 f will prevent excessive sag. note that only the capacitance requirement is increased and the esr requirements don? change. therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-esr capacitor. table 4 summarizes low-voltage operational issues. table 4. low-voltage troubleshooting supply vl from an external source other than v batt , such as the system 5v supply. vl output is so low that it hits the vl uvlo threshold at 4.2v max. low input voltage, <4.5v won? start under load or quits before battery is completely dead use a small 20ma schottky diode for boost diode d2. supply vl from an external source. vl linear regulator is going into dropout and isn? providing good gate-drive levels. low input voltage, <5v high supply current, poor efficiency reduce f to 150khz. reduce secondary impedances?se schottky if possible. stack secondary winding on main output. not enough duty cycle left to initiate forward-mode operation. small ac current in primary can? store energy for flyback operation. low v in -v out differential, v in < 1.3 x v out (main) secondary output won? support a load increase the minimum input voltage or ignore. normal function of internal low- dropout circuitry. low v in -v out differential, <0.5v unstable?itters between two distinct duty factors reduce f to 150khz. reduce mosfet on-resistance and coil dcr. maximum duty-cycle limits exceeded. low v in -v out differential, <0.5v dropout voltage is too high (v out follows v in as v in decreases) increase bulk output capacitance per formula above. reduce inductor value. limited inductor-current slew rate per cycle. low v in -v out differential, <1v sag or droop in v out under step load change solution root cause condition symptom
__________ applications infor mation heavy-load efficiency considerations the major efficiency loss mechanisms under loads (in the usual order of importance) are: p(i 2 r), i 2 r losses p(gate), gate-charge losses p(diode), diode-conduction losses p(tran), transition losses p(cap), capacitor esr losses p(ic), losses due to the operating supply current of the ic inductor-core losses are fairly low at heavy loads because the inductor? ac current component is small. therefore, they aren? accounted for in this analysis. ferrite cores are preferred, especially at 300khz, but powdered cores such as kool-mu can work well. efficiency = p out / p in x 100% = p out / (p out + p total ) x 100% p total = p(i 2 r) + p(gate) + p(diode) + p(tran) + p(cap) + p(ic) p(i 2 r) = (i load ) 2 x (r dc + r ds(on) + r sense ) where r dc is the dc resistance of the coil, r ds(on) is the mosfet on-resistance, and r sense is the current- sense resistor value. the r ds(on) term assumes identi - cal mosfets for the high- and low-side switches because they time-share the inductor current. if the mosfets aren? identical, their losses can be estimat - ed by averaging the losses according to duty factor. p(gate) = gate-driver loss = qg x f x vl where vl is the MAX1652 internal logic supply voltage (5v), and qg is the sum of the gate-charge values for low- and high-side switches. for matched mosfets, qg is twice the data sheet value of an individual mosfet. if v out is set to less than 4.5v, replace vl in this equation with v batt . in this case, efficiency can be improved by connecting vl to an efficient 5v source, such as the system +5v supply. p(diode) = diode conduction losses = i load x v fwd x t d x f where t d is the diode conduction time (120ns typ) and v fwd is the forward voltage of the schottky. pd(tran) = transition loss = v batt x c rss v batt x i load x f x ( ?+ 20ns ) i gate where c rss is the reverse transfer capacitance of the high-side mosfet (a data sheet parameter), i gate is the dh gate-driver peak output current (1a typ), and 20ns is the rise/fall time of the dh driver. p(cap) = input capacitor esr loss = (i rms ) 2 x r esr where i rms is the input ripple current as calculated in the input capacitor value section of the design procedure. light-load efficiency considerations under light loads, the pwm operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. this causes the ac component of the inductor current to be high com - pared to the load current, which increases core losses and i 2 r losses in the output filter capacitors. obtain best light-load efficiency by using mosfets with moderate gate-charge levels and by using ferrite, mpp, or other low-loss core material. avoid powdered iron cores; even kool-mu (aluminum alloy) is not as good as ferrite. __ pc boar d layout considerations good pc board layout is required to achieve specified noise, efficiency, and stability performance. the pc board layout artist must be provided with explicit instructions, preferably a pencil sketch of the place - ment of power switching components and high-current routing. see the evaluation kit pc board layouts in the max1653, max796, and max797 ev kit manuals for examples. a ground plane is essential for optimum per - formance. in most applications, the circuit will be locat - ed on a multilayer board, and full use of the four or more copper layers is recommended. use the top layer for high-current connections, the bottom layer for quiet connections (ref, ss, gnd), and the inner layers for an uninterrupted ground plane. use the following step- by-step guide. 1) place the high-power components (c1, c2, q1, q2, d1, l1, and r1) first, with their grounds adjacent. priority 1: minimize current-sense resistor trace lengths (see figure 9). priority 2: minimize ground trace lengths in the high-current paths (discussed below). priority 3: minimize other trace lengths in the high- current paths. use >5mm wide traces. c1 to q1: 10mm max length. d1 anode to q2: 5mm max length lx node (q1 source, q2 drain, d1 cathode, inductor): 15mm max length ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. these high-current grounds (c1-, c2-, source of q2, anode of d1, and pgnd) are then connected to each other with a wide filled zone MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 24 ______________________________________________________________________________________
of top-layer copper, so that they don? go through vias. the resulting top-layer ?ub-ground-plane?is connected to the normal inner-layer ground plane at the output ground terminals. this ensures that the analog gnd of the ic is sensing at the output termi - nals of the supply, without interference from ir drops and ground noise. other high-current paths should also be minimized, but focusing ruthlessly on short ground and current-sense connections eliminates about 90% of all pc board layout diffi - culties. see the evaluation kit pc board layouts for examples. 2) place the ic and signal components. keep the main switching node (lx node) away from sensitive ana - log components (current-sense traces and ref and ss capacitors). placing the ic and analog compo - nents on the opposite side of the board from the power-switching node is desirable. important: the ic must be no farther than 10mm from the current- sense resistor. keep the gate-drive traces (dh, dl, and bst) shorter than 20mm and route them away from csh, csl, ref, and ss. 3) employ a single-point star ground where the input ground trace, power ground (subground plane), and normal ground plane all meet at the output ground terminal of the supply. MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 25 MAX1652 max1653 max1654 max1655 sense resistor main current path fat, high-current traces figure 9. kelvin connections for the current-sense resistor 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dh lx bst dl gnd ref (secfb) skip ss top view MAX1652 max1653 max1654 max1655 pgnd vl v+ csl ( ) are for MAX1652 / m ax1654. csh fb shdn sync qsop 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dh lx bst dl gnd ref skip ss max1653 max1655 pgnd vl v+ csl csh fb shdn sync narrow so pin configurations
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 26 ______________________________________________________________________________________ transistor count: 1990 ___________________ chip infor mation ________________________________________________________ package infor mation qsop.eps
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop ______________________________________________________________________________________ 27 ___________________________________________ package infor mation (continued) soicn.eps
MAX1652?ax1655 high-ef ficiency , pwm, step-down dc-dc contr ollers in 16-pin qsop 28 ______________________________________________________________________________________ notes

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